* samplenhold
* Converted from CircuitJS by eetree.cn/tools - open in LTspice (File > Open, then Run)
* Suggested traces: V(N002) V(N006)
M1 N002 N001 N003 N004 MP_1p5_20m
D1 N002 N003 D_body
M2 N003 N005 N002 0 MN_1p5_20m
D2 N002 N003 D_body
* logic gate (output 5 V, threshold 2.5 V, ~1 ns delay)
B1 B1x 0 V=5*(1-u(V(N005)-2.5))
RB1 B1x B1y 1k
CB1 B1y 0 1p IC=0
B1o N001 0 V=V(B1y)
* logic input L
V1 N005 0 0
C1 N003 0 100n IC=3.639986843
* op-amp 1: A0=100000, GBW=1000000, output limited to [-15, 15]
G_OA1 0 OA1 N003 N006 1
R_OA1 OA1 0 100k
C_OA1 OA1 0 159.1549431n
B_OA1 N006 0 V=min(max(V(OA1), -15), 15)
V2 N002 0 SIN(2.5 2.5 40 0 0 0)
V3 N004 0 5
.model D_body D(Is=1.7143528192808883e-7 N=2 Rs=1m Cjo=1p)
.model MN_1p5_20m NMOS(Level=1 VTO=1.5 KP=20m)
.model MP_1p5_20m PMOS(Level=1 VTO=-1.5 KP=20m)
.tran 5u 768m 0 5u uic
.end